
/*
 * CPU info struct.  An array of MAX cpus is kept in PSD global mem.
 */

struct _CPUInfo
{
   ulong_t  SlotBaseIOAddr;
   ulong_t  Flags;
   ulong_t  Features;
   ulong_t  ProcessorType;
   ulong_t  Irq;
   ulong_t  Vector;
   ulong_t  reserved;      // BUGBUG get rid of these reserved
   ulong_t  reserved1;
};

typedef struct _CPUInfo S_CPUINFO;
typedef S_CPUINFO *P_CPUINFO;

/*
 * Generate delay between I/O instructions. //BUGBUG - SHOULD BE IMPORTED
 */

#define IODelay {int i; for(i = 0; i < IODelayCount; i++); }

/*
 * Misc.
 */

#define VERSION                  0x00000010

/*
 * CMOS, BIOS, EISA
 */

#define CMOS_ADDR 0x70
#define CMOS_CTRL 0x8F
#define CMOS_DATA 0x71
#define CMOS_WARM 0x0A

#define BIOS_SEG      0xF000
#define BIOS_SEG_SIZE 0x10000

#define EISA_PRODUCT_ID_PORT1 0x0C80  //
#define EISA_PRODUCT_ID_PORT2 0x0C81  //
#define EISA_PRODUCT_ID_PORT3 0x0C82  //
#define EISA_PRODUCT_ID_PORT4 0x0C83  //
/*
 * Tricord Registers
 */

#define MOTHERBOARD_CTRL_REG     0x0C00  // Motherboard control register

#define MBCR_NPX_INT               0x08  // Enable Motherboard NPX int

#define FEATURE_CTRL_REG         0x0C84  // Bit defs below

#define FCR_RESET                0x8000  // CPU reset
#define FCR_INTR                 0x4000  // Interrupt the processor
#define FCR_CACHE_DATA_ONLY      0x2000  // Cache data only
#define FCR_NPX_INT              0x0100  // Enable NPX interrupts
#define FCR_PRI_PIC_INPUT        0x0080  // Enable primary PIC input
#define FCR_INT_MASKING          0x0020  // Enable interrupt masking
#define FCR_L1_CACHE             0x0008  // Enable i486 L1 cache
#define FCR_LOC_NMI              0x0002  // Enable local detected errors to local NMI

#define NOP_VECTOR_REGISTER      0x0C88   // NOP vector and Mask addr register

#define INTERRUPT_MASK_REGISTER  0x0C8C   // Interrupt mask register

#define CPU_STATUS_REGISTER      0x0C90   // Status register - Bit defs below

#define SR_SLOT_ACTIVE           0x0040   // Slot is active

#define NOP_VECTOR   (PIC3_BASE)    // int.h(PIC3_BASE) at PIC3 base
#define NOP_IRQ      0x10           // int.h(PIC3_BASE)

#define MAX_CPUS                       5  //BUGBUG - DOC says 5
                                          //Tricord guys say only 2 CPUs max

#define CPU_BASE_SLOT_BASE_IO_ADDR     0x9000
#define CPU_MAX_SLOT_BASE_IO_ADDR      0xD000


#define UNI_i486_25 0x12        //Processor types
#define UNI_i486_33 0x13
#define MP_i486_25  0x14
#define MP_i486_33  0x15
#define MPC_i486_25 0x16
#define MPC_i486_33 0x17

#define PD_486       0x01  // flag - i486
#define PD_486C      0x02  // flag - i486 w/ L2 cache

#define MP_CPU      0x01    // Flags - CPU is MP
#define L2_CPU      0x02    // Flags - CPU has L2 cache

