;       SCCSID = @(#)debdesc.inc	6.1 90/11/17
;      SCCSID = @(#)debdesc.inc	13.8 89/09/11
;***	DEBDESC.INC
;
;	Definitions for the access byte in a descriptor
;
;

; ---------------------------------------------------
;
; Definitions for the access byte in a descriptor
;
; ---------------------------------------------------


; Following fields are common to segment and control descriptors

D_PRES		equ	080h		; present in memory
D_NOTPRES	equ	0		; not present in memory

D_DPL0		equ	0		; Ring 0
D_DPL1		equ	020h		; Ring 1
D_DPL2		equ	040h		; Ring 2
D_DPL3		equ	060h		; Ring 3
D_PRIV		equ	D_DPL3		; DPL mask

D_SEG		equ	010h		; Segment descriptor
D_CTRL		equ	0		; Control descriptor


; Following fields are specific to control descriptors

D_TSS_BUSY_BIT	equ	02h			; TSS busy bit
D_32		equ	08h			; 32-bit gate/descriptor bit

D_RESERVED0	equ	00h			; 0: reserved
D_TSS		equ	01h			; 1: free TSS
D_LDT		equ	02h			; 2: LDT
D_TSSBUSY	equ	(D_TSS+D_TSS_BUSY_BIT)	; 3: busy TSS
D_CALLGATE	equ	04h			; 4: call gate
D_TASKGATE	equ	05h			; 5: task gate
D_INTGATE	equ	06h			; 6: interrupt gate
D_TRAPGATE	equ	07h			; 7: trap gate
D_RESERVED8	equ	08h			; 8: reserved
D_TSS32		equ	(D_TSS + D_32)		; 9: free 32-bit TSS
D_RESERVEDa	equ	(D_LDT + D_32)		; a: reserved
D_TSSBUSY32	equ	(D_TSSBUSY + D_32)	; b: busy 32-bit TSS
D_CALLGATE32	equ	(D_CALLGATE + D_32)	; c: 32-bit call gate
D_RESERVEDd	equ	(D_TASKGATE + D_32)	; d: reserved
D_INTGATE32	equ	(D_INTGATE + D_32)	; e: 32-bit interrupt gate
D_TRAPGATE32	equ	(D_TRAPGATE + D_32)	; f: 32-bit trap gate

D_TYPEMASK	equ	0fh			; descriptor type mask
D_WCMASK	equ	1fh			; word count mask (call gates)
D_MINGATE	equ	D_CALLGATE		; lowest numerical gate type
D_MAXGATE	equ	D_TRAPGATE		; highest numerical gate type
D_TSSBUSY_CLR	equ	(D_PRES+D_PRIV+D_SEG+D_TSS)


; Following fields are specific to segment descriptors

D_CODE		equ	08h		; code
D_DATA		equ	0		; data

D_CONFORM	equ	04h		; if code, conforming
D_EXPDN		equ	04h		; if data, expand down

D_RX		equ	02h		; if code, readable
D_X		equ	0		; if code, exec only
D_W		equ	02h		; if data, writable
D_R		equ	0		; if data, read only

D_ACCESSED	equ	1		; segment accessed bit


; ---------------------------------------------------
;
; Definitions for the attribute byte in a descriptor
;
; ---------------------------------------------------

D_GRAN4K	equ	80h		; 4k granularity (limit only)
D_COPER32	equ	40h		; code: use 32 bit operand size
D_DBIG		equ	D_COPER32	; data: use 32 bit offsets
D_PAD		equ	20h		; unused
D_UVIRT		equ	10h		; PhysToUvirt selector
D_EXTLIMIT	equ	0fh		; extended limit mask


; Useful combination access rights bytes

D_DATA0		equ	(D_PRES+D_DPL0+D_SEG+D_DATA+D_W)  ; Ring 0 rw data
D_CODE0		equ	(D_PRES+D_DPL0+D_SEG+D_CODE+D_RX) ; Ring 0 rx code
D_TRAP0		equ	(D_PRES+D_DPL0+D_CTRL+D_TRAPGATE) ; Ring 0 trap gate
D_INT0		equ	(D_PRES+D_DPL0+D_CTRL+D_INTGATE)  ; Ring 0 int gate
D_TSS0		equ	(D_PRES+D_DPL0+D_CTRL+D_TSS)	  ; Ring 0 TSS
D_LDT0		equ	(D_PRES+D_DPL0+D_CTRL+D_LDT)	  ; Ring 0 LDT

D_TRAP032	equ	(D_PRES+D_DPL0+D_CTRL+D_TRAPGATE32);Ring 0 32-bit TG
D_INT032	equ	(D_PRES+D_DPL0+D_CTRL+D_INTGATE32); Ring 0 32-bit IG
D_TSS032	equ	(D_PRES+D_DPL0+D_CTRL+D_TSS32)	  ; Ring 0 32-bit TSS

D_DATA1		equ	(D_PRES+D_DPL1+D_SEG+D_DATA+D_W)  ; Ring 1 rw data
D_CODE1		equ	(D_PRES+D_DPL1+D_SEG+D_CODE+D_RX) ; Ring 1 rx code

D_DATA2		equ	(D_PRES+D_DPL2+D_SEG+D_DATA+D_W)  ; Ring 2 rw data
D_CODE2		equ	(D_PRES+D_DPL2+D_SEG+D_CODE+D_RX) ; Ring 2 rx code

D_DATA3		equ	(D_PRES+D_DPL3+D_SEG+D_DATA+D_W)  ; Ring 3 rw data
D_CODE3		equ	(D_PRES+D_DPL3+D_SEG+D_CODE+D_RX) ; Ring 3 rx code

D_INT3		equ	(D_PRES+D_DPL3+D_CTRL+D_INTGATE)  ; Ring 3 int gate
D_GATE3		equ	(D_PRES+D_DPL3+D_CTRL+D_CALLGATE) ; Ring 3 call gate
D_INT332	equ	(D_PRES+D_DPL3+D_CTRL+D_INTGATE32); Ring 3 32-bit IG
D_GATE332	equ	(D_PRES+D_DPL3+D_CTRL+D_CALLGATE32);Ring 3 32-bit CG

; Definitions for selector fields

SELECTOR_MASK	equ    0fff8h		; selector index
SEL_LOW_MASK	equ	 0f8h		; mask for low byte of sel indx
PRIVATE_MASK	equ	0000h		; private LDT bit (documentation only)
SHARE_MASK	equ	0018h		; shared LDT bits
TABLE_MASK	equ	0004h		; table bit
RPL_MASK	equ	0003h		; privilege bits
RPL_CLR		equ	(not RPL_MASK)	; clear ring bits
RPL_RING0	equ	0000h		; ring 0 requested
RPL_RING1	equ	0001h		; ring 1 requested
RPL_RING2	equ	0002h		; ring 2 requested
RPL_RING3	equ	0003h		; ring 3 requested

; CR0 (Machine Status Register) bits

CR0_PE		equ	00000001h	; (P)rotect (E)nable
CR0_MP		equ	00000002h	; (M)onitor (P)rocessor extension
CR0_EM		equ	00000004h	; (EM)ulate processor extension
CR0_TS		equ	00000008h	; (T)ask (thread) (S)witched
CR0_ET		equ	00000010h	; (E)xtension (T)ype, 0/1=287/387
CR0_NE		equ	00000020h	; (N)umeric (E)xception 0/1=use 2/10h

; High word of CR0 bits

CR0HI_WP	equ	0001h		; (W)rite (P)rotect in rings 0-2
CR0HI_AM	equ	0004h		; (A)lignment (M)ask, enable EFlags.AC
CR0HI_WT	equ	2000h		; cache (W)rites (T)ransparent
CR0HI_CE	equ	4000h		; (C)ache (E)nable
CR0HI_PG	equ	8000h		; (P)a(G)ing enable


; --------------------------------------------------
;
; Descriptor and gate structures
;
; --------------------------------------------------

Desc	struc
	DescLimit	dw	0		; limit (size - 1)
	DescBaseLow	dw	0		; bits 0-15 of base address
	DescBaseHigh	db	0		; bits 16-23 of base address
	DescAccess	db	0		; access byte
	DescAttr	db	0		; attributes/extended limit
	DescBaseExt	db	0		; bits 24-31 of base address
Desc	ends

DAC	record	DAC_PRESENT:1,	  \
		DAC_DPL:2,	  \
		DAC_SEG_CTRL:1,	  \
		DAC_CODE_DATA:1,  \
		DAC_CONFORMING:1, \
		DAC_READCODE:1,	  \
		DAC_ACCESS:1

DAC_WRITEDATA	equ	<DAC_READCODE>		; read/write data
DAC_EXPANDDOWN	equ	<DAC_CONFORMING>	; expand down data

DAT	record	DAT_G:1,	  \
		DAT_D:1,	  \
		DAT_RES:1,	  \
		DAT_AVAL:1,	  \
		DAT_LIMIT:4			; bits 19 - 16 of limit

DAT_B		equ	<DAT_D>			; big bit (for data segments)

Gate	struc
	GateOffset	dw	0		; gate offset
	GateSelector	dw	0		; gate selector
	GateWordCount	db	0		; word count for call gate
	GateAccess	db	0		; access byte
	GateExtOffset	dw	0		; extended target offset
Gate	ends

GWC	record	GWC_RES:3,GWC_COUNT:5
GA	record	GA_PRESENT:1,GA_DPL:2,GA_CTRL:1,GA_TYPE:4

; -----------------------------------------------------
;
; Load/store gdt/idt register instruction buffer structure
;
; -----------------------------------------------------

DTR	struc
	DTRLimit	dw	0		; limit of gdt/idt register
	DTRBaseLow	dw	0		; bits 0-15 of base address
	DTRBaseHigh	db	0		; bits 16-23 of base address
	DTRBaseExt	db	0		; bits 24-31 of base address
DTR	ends

DTRBaseHighExt		equ	(word ptr DTRBaseHigh)

; -----------------------------------------------------
;
; 386 TSS (Task state segment) structure.
;
; -----------------------------------------------------

tss_s struc
	tss_backlink	dw	0		; backlink to prev task (none)
			dw	?
	tss_esp0	dd	0
	tss_ss0		dw	0		; ring 0 ss
			dw	?
	tss_esp1	dd	0		; ring 1 esp
	tss_ss1		dw	0		; ring 1 ss
			dw	?
	tss_esp2	dd	0		; ring 2 esp
	tss_ss2		dw	0		; ring 2 ss
			dw	?
	tss_cr3		dd	?
	tss_eip		dd	0		; entry point
	tss_eflags	dd	0		; eflags
	tss_eax		dd	0
	tss_ecx		dd	0
	tss_edx		dd	0
	tss_ebx		dd	0
	tss_esp		dd	0
	tss_ebp		dd	0
	tss_esi		dd	0
	tss_edi		dd	0
	tss_es		dw	0
			dw	?
	tss_cs		dw	0
			dw	?
	tss_ss		dw	0
			dw	?
	tss_ds		dw	0
			dw	?
	tss_fs		dw	0
			dw	?
	tss_gs		dw	0
			dw	?
	tss_ldt		dw	0
			dw	?
	tss_tflags	dw	0
	tss_iomap	dw	-1		; I/O map TSS relative offset
tss_s ends

;	tss_tflags bit definitions:

TSS_DEBUGTRAP	equ	0001h	; raise debug exception on task switch


; -----------------------------------------------------
;
; 386 TSS (Task state segment) structure.
;
; -----------------------------------------------------

tss16_s struc
	tss16_backlink	dw	0		; backlink to prev task (none)
	tss16_sp0	dw	0		; ring 0 sp
	tss16_ss0	dw	0		; ring 0 ss
	tss16_sp1	dw	0		; ring 1 sp
	tss16_ss1	dw	0		; ring 1 ss
	tss16_sp2	dw	0		; ring 2 sp
	tss16_ss2	dw	0		; ring 2 ss
	tss16_ip	dw	0		; entry point
	tss16_flags	dw	0		; flags
	tss16_ax	dw	0
	tss16_cx	dw	0
	tss16_dx	dw	0
	tss16_bx	dw	0
	tss16_sp	dw	0
	tss16_bp	dw	0
	tss16_si	dw	0
	tss16_di	dw	0
	tss16_es	dw	0
	tss16_cs	dw	0
	tss16_ss	dw	0
	tss16_ds	dw	0
	tss16_ldt	dw	0
tss16_s ends

; physical address of loadall buffer

LOADALL_ADDR	equ	800h

; -----------------------------------------------------
;
; Descriptor Cache structure (used in loadall buffer)
;
; -----------------------------------------------------

DescCache	struc
	CacheBaseLow	dw	?
	CacheBaseHigh	db	?
	CacheAccess	db	?
	CacheLimit	dw	?
DescCache	ends

; -----------------------------------------------------
;
; Loadall buffer structure
;
; -----------------------------------------------------

LoadAllStruc	struc
	loadall_none1	db	6 dup(?)
	loadall_MSW	dw	?
	loadall_none2	db	14 dup(?)
	loadall_TR	dw	?
	loadall_FLAGS	dw	?
	loadall_IP	dw	?
	loadall_LDTR	dw	?
	loadall_DS	dw	?
	loadall_SS	dw	?
	loadall_CS	dw	?
	loadall_ES	dw	?
	loadall_DI	dw	?
	loadall_SI	dw	?
	loadall_BP	dw	?
	loadall_SP	dw	?
	loadall_BX	dw	?
	loadall_DX	dw	?
	loadall_CX	dw	?
	loadall_AX	dw	?
	loadall_EScache	db	size DescCache dup(?)
	loadall_CScache	db	size DescCache dup(?)
	loadall_SScache	db	size DescCache dup(?)
	loadall_DScache	db	size DescCache dup(?)
	loadall_GDTR	db	size DescCache dup(?)
	loadall_LDTcache db	size DescCache dup(?)
	loadall_IDTR	db	size DescCache dup(?)
	loadall_TRcache	db	size DescCache dup(?)
LoadAllStruc	ends

.386p
PAGESHIFT	equ	12
PAGESIZE	equ	(1 shl PAGESHIFT)

;*  32 bit linear address composition:
;
;   dddddddddd				10 bit page directory entry index
;	      tttttttttt		10 bit page table entry index
;			oooooooooooo	12 bit page data offset

Lin	record	LinPageDir:10, LinPageTable:10, LinDataOffset:12


;*  32 bit physical address composition:
;
;   ffffffffffffffffffff		20 bit page frame address
;			oooooooooooo	12 bit page data offset

Phy	record	PhyPageFrame:20, PhyDataOffset:12


;*   Page directory and table entry definations

PTE	record	PTE_PageFrame:20,   \
		PTE_Aval:3,	    \
		PTE_Res:2,	    \
		PTE_Dirty:1,	    \
		PTE_Accessed:1,	    \
		PTE_CacheDisable:1, \
		PTE_WriteThrough:1, \
		PTE_User:1,	    \
		PTE_Write:1,	    \
		PTE_Present:1

PTE_SHIFT	equ	2
.286p

IFNDEF INCL_MI

;*   Debug register (DR0 - DR7) definations

DR7High	record	DR3_LEN:2,  \
		DR3_TYPE:2, \
		DR2_LEN:2,  \
		DR2_TYPE:2, \
		DR1_LEN:2,  \
		DR1_TYPE:2, \
		DR0_LEN:2,  \
		DR0_TYPE:2

DR7Low	record	DR7_Res:6,  \
		DR7_GE:1,   \
		DR7_LE:1,   \
		DR7_G3:1,   \
		DR7_L3:1,   \
		DR7_G2:1,   \
		DR7_L2:1,   \
		DR7_G1:1,   \
		DR7_L1:1,   \
		DR7_G0:1,   \
		DR7_L0:1

DR6Low	record	DR6_BT:1,   \
		DR6_BS:1,   \
		DR6_BD:1,   \
		DR6_Res:9,  \
		DR6_B3:1,   \
		DR6_B2:1,   \
		DR6_B1:1,   \
		DR6_B0:1

DR7_LEN_1		equ	00000000b	; one-byte length
DR7_LEN_2		equ	00000001b	; word length
DR7_LEN_4		equ	00000011b	; dword length

DR7_TYPE_EXECUTE	equ	00000000b	; break on instr execute only
DR7_TYPE_WRITE		equ	00000001b	; break on data writes only
DR7_TYPE_IO		equ	00000010b	; break on i/o read/writes	; 148688
DR7_TYPE_RW		equ	00000011b	; break on read/writes only

NUM_DEBUG_REG		equ	4		; number of debug registers

ENDIF ; INCL_MI
