/*

    Copyright (C) Corollary, Inc., 1993, 1994.
    All Rights Reserved.
    This Module contains Proprietary Information of
    Corollary, Inc., and should be treated as Confidential.

Module Name:

    cbus.h

Abstract:

    Cbus architecture definitions for the Corollary C-bus I & II
    multiprocessor PSD modules.  The common hardware definitions
    needed for the OS/2 2.x PSD reside here.  Hardware
    architecture-specific definitions are in their respective modules.

Author:

    Landy Wang (landy@corollary.com) 11-Jan-1994
 */

#ifndef _CBUS_
#define _CBUS_

#include <sys/types.h>

/*
 *  used to read/write the current task priority.  reads DO NOT
 *  have to be AND'ed with 0xff - this register has been
 *  guaranteed by both Corollary (for the CBC) and Intel
 *  (for the APIC) so that bits 8-31 will always read zero.
 *  (The Corollary guarantee is written, the Intel is verbal).
 *
 *  note that this definition is being used both for the
 *  64-bit CBC and the 32-bit APIC, even though the APIC
 *  really only has the low 32 bits.
 *
 *  Task Priority ranges from a low of 0 (all interrupts unmasked)
 *  to a high of 0xFF (all interrupts masked) on both CBC and APIC.
 */
typedef union _taskpri_t {
        struct {
                ULONG   pri : 8;
                ULONG   zero : 24;
                ULONG   reserved1 : 32;
        } ra;
        struct {
                ULONG   low_dword;
                ULONG   high_dword;
        } rb;
} TASKPRI_T, *PTASKPRI;

/*
 * max number of C-bus II elements & processors.
 * (processors == elements - broadcast element).
 */

#define MAX_ELEMENT_CSRS        15
#define MAX_CBUS_ELEMENTS       (MAX_ELEMENT_CSRS + 1)

typedef struct _element_t {
        ULONG           Status; /* opaque pointer to this CPU's CSR */
        PVOID           csr;    /* opaque pointer to this CPU's CSR */
        PVOID           idp;    /* opaque pointer to this CPU's RRD info entry */
} ELEMENT_T, PELEMENT;

extern ELEMENT_T        CbusCSR[];

#define CPU_BOOTED      0x1
#define CPU_ACTIVE      0x2     /* turned on when enabled, off when disabled */

extern ULONG CbusActiveProcessors;
extern ULONG CbusActiveProcessorsMask;

/*
 * list of memory boards in the system
 */
typedef struct _memory_card_t {

        PULONG          regmap;
        ULONG           io_attr;

} MEMORY_CARD_T, *PMEMORY_CARD;

extern MEMORY_CARD_T    CbusMemoryBoards [MAX_ELEMENT_CSRS];
extern ULONG            CbusMemoryBoardIndex;

#define EISA_IRQLINES   16

#define MAX_VECTORS             256

extern BOOL		CbusVirtualWire;
/*
 * bit value for the Polarity structure...
 */
#define EDGE_TRIGGERED          0x0
#define LEVEL_TRIGGERED         0x1

/*
 * send the interrupt to the lowest-in-group processor
 */
#define SHOOT_LIG       ((ULONG)-1)

#define COUTB(addr, reg, val) (((PUCHAR)(addr))[reg] = (UCHAR)val)
#define COUTD(addr, reg, val) ((PULONG)(((PUCHAR)(addr))[reg]) = (ULONG)val)

extern CBUS_PRIVATE     *CbusPerCPU;

/*
 * there really is no irq associated with spurious or IPI vectors - we need
 * the definitions below because the OS/2 kernel needs some kind of irq number
 * as a parameter to the PSD help functions.
 */
#define SPURIOUS_IRQ            0x1F
#define IPI_IRQ                 0x1E

/*
 * the vector definition below is definitely needed for the hardware.  this
 * is so the hardware knows what vector to generate to the processor when
 * the specific event occurs.
 */
#define SPURIOUS_VECTOR         0xFF
#define IPI_VECTOR              0xE0

/*
 * we give irqlines 0-15 the vectors 0x30-0x3f.  no need to map them down
 * during interrupt receipt - no OS/2 drivers use (or get?) the value.
 *
 * 0x30-0x3f, 0x50-0x5f, 0x70-0x77, 0x80-0x87 are reserved by the OS/2 kernel.
 */

#define NO_IRQLINE              0xFF

#endif      /* _CBUS_ */
