;       SCCSID = @(#)int.inc	6.1 90/11/17

;***	INT.INC
;
;	SCCSID = @(#)int.inc	1.11 90/09/27
;
;	Title:
;
;	Interrupt Management Include File
;
;	IBM/Microsoft Confidential
;
;	Copyright (c) IBM Corporation 1987, 1989
;	Copyright (c) Microsoft Corporation 1987, 1989
;
;	All Rights Reserved
;

;*	Misc. PIC definations

NUMBER_PICS			equ	2
NUM_IRQ_PER_PIC			equ	8
NUM_IRQ				equ	(NUMBER_PICS * NUM_IRQ_PER_PIC)
MAX_IRQ				equ	32
PIC_SLAVE_IRQ			equ	2
DWORD_ALIGN_MASK		equ	(not 3)

PIC1_OLD_BASE			equ	08h
PIC2_OLD_BASE			equ	70h

PIC1_NEW_BASE			equ	50h
PIC2_NEW_BASE			equ	70h

;*	PIC port definations

PIC1_PORT0			equ	20h		; master PIC
PIC1_PORT1			equ	21h
PIC2_PORT0			equ	0A0h		; slave PIC
PIC2_PORT1			equ	0A1h

;*	Initialization control words equates for the PICs

ICW1_ICW4_NEEDED		equ	00000001b
ICW1_NO_ICW4_NEEDED		equ	00000000b
ICW1_SINGLE			equ	00000010b
ICW1_CASCADE			equ	00000000b
ICW1_INTERVAL4			equ	00000100b
ICW1_INTERVAL8			equ	00000000b
ICW1_LEVEL_TRIG			equ	00001000b
ICW1_EDGE_TRIG			equ	00000000b
ICW1_ICW			equ	00010000b

ICW4_8086_MODE			equ	00000001b
ICW4_8085_MODE			equ	00000000b
ICW4_AUTO_EOI			equ	00000010b
ICW4_NORM_EOI			equ	00000000b
ICW4_NON_BUF_MODE		equ	00000000b
ICW4_BUF_MODE_SLAVE		equ	00001000b
ICW4_BUF_MODE_MASTER		equ	00001100b
ICW4_SPEC_FULLY_NESTED		equ	00010000b
ICW4_NOT_SPEC_FULLY_NESTED	equ	00000000b

;*	Output Control Words for the 8259 PIC

OCW2_NON_SPECIFIC_EOI		equ	00100000b
OCW2_SPECIFIC_EOI		equ	01100000b
OCW2_SET_PRIORITY		equ	11000000b

OCW3_READ_IRR			equ	00001010b
OCW3_READ_ISR			equ	00001011b

;   The In Service Register Masks are used to test the output from
;   the GetISR function call

;   In Service Register Mask for the Master 8259

ISR_IRQ0			equ	00000000000000000000000000000001b
ISR_IRQ1			equ	00000000000000000000000000000010b
ISR_IRQ2			equ	00000000000000000000000000000100b
ISR_IRQ3			equ	00000000000000000000000000001000b
ISR_IRQ4			equ	00000000000000000000000000010000b
ISR_IRQ5			equ	00000000000000000000000000100000b
ISR_IRQ6			equ	00000000000000000000000001000000b
ISR_IRQ7			equ	00000000000000000000000010000000b

;   In-Service Register Mask for the Slave 8259

ISR_IRQ8			equ	00000000000000000000000100000000b
ISR_IRQ9			equ	00000000000000000000001000000000b
ISR_IRQA			equ	00000000000000000000010000000000b
ISR_IRQB			equ	00000000000000000000100000000000b
ISR_IRQC			equ	00000000000000000001000000000000b
ISR_IRQD			equ	00000000000000000010000000000000b
ISR_IRQE			equ	00000000000000000100000000000000b
ISR_IRQF			equ	00000000000000001000000000000000b

;   In Service Register Mask for the Third 8259

ISR_IRQ10			equ	00000000000000010000000000000000b
ISR_IRQ11			equ	00000000000000100000000000000000b
ISR_IRQ12			equ	00000000000001000000000000000000b
ISR_IRQ13			equ	00000000000010000000000000000000b
ISR_IRQ14			equ	00000000000100000000000000000000b
ISR_IRQ15			equ	00000000001000000000000000000000b
ISR_IRQ16			equ	00000000010000000000000000000000b
ISR_IRQ17			equ	00000000100000000000000000000000b

;   In-Service Register Mask for the Fourth 8259

ISR_IRQ18			equ	00000001000000000000000000000000b
ISR_IRQ19			equ	00000010000000000000000000000000b
ISR_IRQ1A			equ	00000100000000000000000000000000b
ISR_IRQ1B			equ	00001000000000000000000000000000b
ISR_IRQ1C			equ	00010000000000000000000000000000b
ISR_IRQ1D			equ	00100000000000000000000000000000b
ISR_IRQ1E			equ	01000000000000000000000000000000b
ISR_IRQ1F			equ	10000000000000000000000000000000b

;* IRQ Numbers

IRQ0		EQU	0
IRQ1		EQU	1
IRQ2		EQU	2
IRQ3		EQU	3
IRQ4		EQU	4
IRQ5		EQU	5
IRQ6		EQU	6
IRQ7		EQU	7

IRQ8		EQU	8
IRQ9		EQU	9
IRQA		EQU	10
IRQB		EQU	11
IRQC		EQU	12
IRQD		EQU	13
IRQE		EQU	14
IRQF		EQU	15

IRQ10		EQU	16
IRQ11		EQU	17
IRQ12		EQU	18
IRQ13		EQU	19
IRQ14		EQU	20
IRQ15		EQU	21
IRQ16		EQU	22
IRQ17		EQU	23

IRQ18		EQU	24
IRQ19		EQU	25
IRQ1A		EQU	26
IRQ1B		EQU	27
IRQ1C		EQU	28
IRQ1D		EQU	29
IRQ1E		EQU	30
IRQ1F		EQU	31

;*	Size of interrupt-time stack in bytes

IFDEF	PMDEBUG
INT_STACK_SIZE			equ	4096	; 4K Stack for debug kernel
MAX_STACK_LIMIT			equ	10240	; 10K max for kernel debugger
ELSE
INT_STACK_SIZE			equ	2048	; 2K Stack for normal kernel
MAX_STACK_LIMIT			equ	8192	; 8K max for normal debugger
ENDIF

INT_STACK_FILL			equ	0cch	; stack fill byte
TEMP_STACK_SIZE			equ	8192	; 8K temporary stack

;***LT+ irqi - IRQ information block
;
;	This structure contains the per IRQ information for each
;	interrupt level.  Each entry contains information
;	like flags and the head of the shared DD information block.
;

irqi	struc
	irqi_pdirqHead	dd	?	; Head of shared DD chain (0 = not set)
	irqi_usIRQNum	dw	?	; IRQ number
	irqi_usFlags	dw	?	; IRQ Flags
irqi	ends
;end

;***LT+ irqi_usFlags bit field definition
;
;	This is the IRQ flag field definition.
;
;	irqf_fVDM     If set, this IRQ is a candidate for routing
;		      to a VDM, if it is not claimed by a dd
;
;	irqf_fNPX     If set, the IRQ is the NPX interrupt level
;
;	irqf_fSharing If set, the IRQ is sharable.  If clear the
;		      IRQ can not be shared by DD.
;
;	irqf_fSys     If set, the IRQ is owned by the system and
;		      the handler can not be changed or removed by
;		      a device driver.  Set initially for the slave,
;		      IRQ 2.
;
;	irqf_fShared  If set, the IRQ can be shared by more than 1
;		      DD.  This bit reflects the shared parameter of
;		      the first dh_SetIRQ issued for this level.
;

irqf	record irqf_Reserved:11, irqf_fVDM:1, irqf_fNPX:1, irqf_fSharing:1, irqf_fSys:1, irqf_fShared:1
;end

;***LT+ dirq - Device IRQ information block
;
;	This structure contains the device driver specific data for
;	an IRQ.  On a shared interrupt machine, the interrupt manager
;	allows more than one device driver to register an IRQ handler.
;	This data structure is allocated for each device driver that
;	register a particular IRQ.
;

dirq	struc
	dirq_pdirqLink		dd	?	; Next DIRQ structure in list
	dirq_f16pfn		dd	?	; DD's interrupt handler
	dirq_usDS		dw	?	; DD's data segment
	dirq_usIRQNum		dw	?	; IRQ number
	dirq_pdirqFreeList	dd	?	; list of unset DIRQs
dirq	ends
;end

;***ET+ StackUsage - Stack usage devhlp input structure
;
;	su_cbStruct	number of bytes in structure including itself.
;
;	su_flags	bit 0x0001 on indicates that the interrupt
;			procedure enables interrupts. All others are
;			reserved.
;
;	su_iIRQ		IRQ of interrupt handler that is being
;			described by the following data.
;
;	su_cbStackCLI	number of bytes of stack used in the interrupt
;			procedure when interrupts are off.
;
;	su_cbStackSTI	number of bytes of stack used after interrupt
;			procedure enables interrupts.
;
;	su_cbStackEOI	number of bytes of stack used after interrupt
;			procedure issues EOI.
;
;	su_cNest	maximum number of levels that the device
;			driver expects to nest.
;

STACK_USAGE_SIZE	equ	  14

StackUsage		struc
	su_cbStruct	dw	  STACK_USAGE_SIZE
	su_flags	dw	  0		 ; bit 1 = enable interrupts
	su_iIRQ		dw	  0		 ; IRQ of DD that registers
	su_cbStackCLI	dw	  0		 ; # bytes used while disabled
	su_cbStackSTI	dw	  0		 ; # bytes used while enabled
	su_cbStackEOI	dw	  0		 ; # bytes used after EOI
	su_cNest	dw	  0		 ; nesting level
StackUsage		ends

;	Flag bits for SU_flags

SU_ENABLE		equ	  0001h
;end
.erre ((size StackUsage) eq (STACK_USAGE_SIZE))

InterruptTable	struc
ITCount		db	?
ITHVector	db	?
ITMappedVector	db	?
InterruptTable	ends
