
/*
 * Miscellaneous
 */

#define VERSION   0x00000010

#define _64K      (64 * 1024)

#define BIOS_SEG             0xF000
#define EISA_STRING_OFFSET   0xFFD9
#define COMPAQ_STRING_OFFSET 0xFFEA

#define CPU0  0x00
#define CPU1  0x01
#define CPU2  0x02
#define CPU3  0x03
#define CPU4  0x04
#define CPU5  0x05
#define CPU6  0x06
#define CPU7  0x07

#define MAXCPU  8


/*
 * PLMA structure
 */

typedef struct plma_s {
   ulong_t logical_procnum;  /* Current logical processor number (0-based) */
   ulong_t physical_procnum; /* Current physical processor number (0-based) */
} PLMA;


/*
 * Generate delay between I/O instructions
 */

#define IODelay {int i; for(i = 0; i < IODelayCount; i++); }


/*
 * IPI info
 */

#define IPI_IRQ       0x0d                 /* IRQ level for IPI */
#define IPI_IRQ_PORT  IRQD_CONTROL_STATUS  /* IRQ_CONTROL_STATUS port for IPI */
#define IPI_VECTOR    0x75                 /* Vector number for IPI */


/*
 * The following ports contain the EISA identification of the
 * system processor boards
 */

#define COMPAQ_ID1  0x0000000E
#define COMPAQ_ID2  0x00000011

#define EISA_PRODUCT_ID_PORT1  0x0C80  /* Compressed COMPAQ ID - OEh */
#define EISA_PRODUCT_ID_PORT2  0x0C81  /*                        11h */
#define EISA_PRODUCT_ID_PORT3  0x0C82  /* Product code for the proc board */
#define EISA_PRODUCT_ID_PORT4  0x0C83  /* Revision number */

#define BELIZE_MASK  0x05


/*
 * The CPU mode select port, controls wether the machine will
 * operate in Belize, or SystemPro compatible mode.
 * Access: Global
 */

#define CPU_MODE_SELECT_PORT  0x0C67
#define BELIZE_MODE_MASK     0x20


/*
 * The contents of the WHO_AM_I port (read-only) can be used
 * by code to determine which logical processor we are
 * currently on.
 * Access: Local
 */

#define WHO_AM_I_PORT  0xC70


/*
 * The CPU index port specifies which physical CPU to access when
 * software reads or writes the logical CPU assignment port.
 * This port is also used to specify the logical CPU to access
 * during an indexed I/O cycle.
 * Access: Global
 */

#define CPU_INDEX_PORT  0x0C74


/*
 * The Logical CPU assignment port is used to assign a logical CPU
 * number for a physical CPU. Software specifies the physical CPU
 * to receive assignment by writing to the CPU index port.
 * This port can also be used to determine logical processor assignment.
 * Access: Indexed
 */

#define LOGICAL_CPU_ASSIGNMENT_PORT  0x0C71

#define PROC_NOT_PRESENT  0x5E


/*
 * The Index I/O registers provide the ability for one CPU to
 * perform I/O reads and writes to another CPU's local registers.
 * Access: Global
 */

#define INDEX_ADDRESS_REGISTER_LOWBYTE   0x0C75
#define INDEX_ADDRESS_REGISTER_HIGHBYTE  0x0C76
#define INDEX_DATA_REGISTER              0x0C77


/*
 * The CPU control ports is used to control the execution, and check
 * the status of the system CPU's.
 * Access: Local or Indexed
 */

#define CPU_CONTROL_PORT  0x0C6A

struct _b_read_cpucontrol_s {

   ulong_t _pad:1,        /* Reserved */

           _NPXpres:1,    /* Numeric Coprocessor installed */
                          /*  0 = NPX is not installed */
                          /*  1 = NPX is installed */

           _cachestat:1,  /* Cache Status */
                          /*  0 = Primary and secondary caches are disabled */
                          /*  1 = Primary and secondary caches are enabled */

           _sleepstat:1,  /* Sleep Status */
                          /*  0 = CPU is awake */
                          /*  1 = CPU is sleeping */

           _pad1:1,       /* Reserved */

           _NPXstat:1,    /* Numeric coprocessor status */
                          /*  0 = No numeric coprocessor error*/
                          /*  1 = Numeric coprocessor error occurred */
                          /*      must be cleared by software */

           _pad2:2,       /* Reserved */

           _pad3:24;      /* Unused */
};

struct _b_write_cpucontrol_s {

   ulong_t _sleepset:1,   /* Sleep set */
                          /*  0 = Ignored */
                          /*  1 = Assert sleep to CPU */

           _sleepclear:1, /* Sleep clear */
                          /*  0 = Ignored */
                          /*  1 = De-assert sleep to CPU */

           _cacheena:1,   /* Cache Enable */
                          /*  0 = Ignored */
                          /*  1 = Enable primary and secondary caches */

           _cachedis:1,   /* Cache Disable */
                          /*  0 = Ignored */
                          /*  1 = Disable primary and secondary caches */

           _cacheflush:1, /* Cache Flush */
                          /*  0 = Ignored */
                          /*  1 = Flush primary and secondary caches */

           _reset:1,      /* Reset CPU */
                          /*  0 = Ignored */
                          /*  1 = Generate a reset pulse on processor */

           _pad2:2,       /* Reserved */

           _pad3:24;      /* Unused */
};

struct _l_cpucontrol_s {
    unsigned long _long;
};

union _cpucontrol_u {
    struct _b_read_cpucontrol_s  b_read_cpucontrol_s;
    struct _b_write_cpucontrol_s b_write_cpucontrol_s;
    struct _l_cpucontrol_s       l_cpucontrol_s;
};

struct cpucontrol_s {
    union _cpucontrol_u cpucontrol_u;
};

#define b_NPXpres     cpucontrol_u.b_read_cpucontrol_s._NPXpres
#define b_cachestat   cpucontrol_u.b_read_cpucontrol_s._cachestat
#define b_sleepstat   cpucontrol_u.b_read_cpucontrol_s._sleepstat
#define b_NPXstat     cpucontrol_u.b_read_cpucontrol_s._NPXstat
#define b_sleepset    cpucontrol_u.b_write_cpucontrol_s._sleepset
#define b_sleepclear  cpucontrol_u.b_write_cpucontrol_s._sleepclear
#define b_cacheena    cpucontrol_u.b_write_cpucontrol_s._cacheena
#define b_cachedis    cpucontrol_u.b_write_cpucontrol_s._cachedis
#define b_cacheflush  cpucontrol_u.b_write_cpucontrol_s._cacheflush
#define b_reset       cpucontrol_u.b_write_cpucontrol_s._reset
#define b_cpu_all     cpucontrol_u.l_cpucontrol_s._long


/*
 * The IRQ control/status ports provide control and status
 * information for interprocessor interrupts.
 * Access: Local or Indexed
 */

#define IRQ0_CONTROL_STATUS  0x0CB0
#define IRQ1_CONTROL_STATUS  0x0CB2
#define IRQ3_CONTROL_STATUS  0x0CB4
#define IRQ4_CONTROL_STATUS  0x0CB6
#define IRQ5_CONTROL_STATUS  0x0CB8
#define IRQ6_CONTROL_STATUS  0x0CBA
#define IRQ7_CONTROL_STATUS  0x0CBC
#define IRQ8_CONTROL_STATUS  0x0CBE
#define IRQ9_CONTROL_STATUS  0x0CC0
#define IRQA_CONTROL_STATUS  0x0CC2
#define IRQB_CONTROL_STATUS  0x0CC4
#define IRQC_CONTROL_STATUS  0x0CC6
#define IRQD_CONTROL_STATUS  0x0CC8
#define IRQE_CONTROL_STATUS  0x0CCC
#define IRQF_CONTROL_STATUS  0x0CCE

struct _b_read_irqcontrol_s {

   ulong_t _pintreq:1,    /* PINT request */
                          /*  0 = no CPU PINT requested at this level */
                          /*  1 = CPU PINT requested at this level */

           _pintstat:1,   /* PINT stat */
                          /*  0 = CPU PINT not enabled at this level */
                          /*  1 = CPU PINT enabled at this level */

           _pad:6,        /* Reserved */

           _pad1:24;      /* Unused */
};

struct _b_write_irqcontrol_s {

   ulong_t _pintset:1,    /* PINT set */
                          /*  0 = No effect on CPU PINT at this level */
                          /*  1 = Set CPU PINT at this level if enabled */

           _pintclear:1,  /* PINT clear */
                          /*  0 = Do not effect CPU PINT at this level */
                          /*  1 = Clear CPU PINT at this level */

           _pintena:1,    /* PINT Enable */
                          /*  0 = No effect of CPU PINT enable for this level */
                          /*  1 = Enable CPU PINT at this level */

           _pintdis:1,    /* PINT Disable */
                          /*  0 = No effect of CPU PINT disable for this level*/
                          /*  1 = Disable CPU PINT at this level */

           _pad:4,        /* Reserved */

           _pad1:24;      /* Unused */
};

struct _l_irqcontrol_s {
    unsigned long _long;
};

union _irqcontrol_u {
    struct _b_read_irqcontrol_s  b_read_irqcontrol_s;
    struct _b_write_irqcontrol_s b_write_irqcontrol_s;
    struct _l_irqcontrol_s       l_irqcontrol_s;
};

struct irqcontrol_s {
    union _irqcontrol_u irqcontrol_u;
};

#define b_pintreq     irqcontrol_u.b_read_irqcontrol_s._pintreq
#define b_pintstat    irqcontrol_u.b_read_irqcontrol_s._pintstat
#define b_pintset     irqcontrol_u.b_write_irqcontrol_s._pintset
#define b_pintclear   irqcontrol_u.b_write_irqcontrol_s._pintclear
#define b_pintena     irqcontrol_u.b_write_irqcontrol_s._pintena
#define b_pintdis     irqcontrol_u.b_write_irqcontrol_s._pintdis
#define b_irq_all     irqcontrol_u.l_irqcontrol_s._long


/*
 * The Extended IRQ13 control/status ports provide control and status
 * information for IRQ13. IRQ13 is shared by the numeric coprocessor
 * error interrupt, DMA chaining interrupt, and correctable error
 * interrupt.
 * Access: Local or Indexed
 */

#define EXTENDED_IRQD_CONTROL_STATUS  0x0CC9

struct _b_read_eirqcontol_s {

   ulong_t _ncpact:1,     /* Numeric coprocessor error interrupt active */
                          /*  0 = NCP error interrupt not active */
                          /*  1 = NCP error interrupt active */

           _ncpstat:1,    /* Numeric coprocessor error interrupt status */
                          /*  0 = NCP error interrupt not enabled */
                          /*  1 = NCP error interrupt enabled */

           _DMAact:1,     /* DMA chaining interrupt active */
                          /*  0 = DMA chaining interrupt not active */
                          /*  1 = DMA chaining interrupt active */

           _DMAstat:1,    /* DMA chaining interrupt status */
                          /*  0 = DMA chaining interrupt not enabled */
                          /*  1 = DMA chaining interrupt enabled */

           _cmeact:1,     /* Correctable memory error interrupt active */
                          /*  0 = CME interrupt not active */
                          /*  1 = CME interrupt active */

           _cmestat:1,    /* Correctable memory error status */
                          /*  0 = CME interrupt not enabled */
                          /*  1 = CME interrupt enabled */

           _pad:2,        /* Reserved */

           _pad1:24;      /* Unused */
};

struct _b_write_eirqcontol_s {

   ulong_t _ncpena:1,     /* Numeric coprocessor error interrupt enable */
                          /*  0 = No effect */
                          /*  1 = Enable NCP error interrupt */

           _ncpdis:1,     /* Numeric coprocessor error interrupt disable */
                          /*  0 = No effect */
                          /*  1 = Disable NCP error interrupt */

           _DMAena:1,     /* DMA chaining interrupt enable */
                          /*  0 = No effect */
                          /*  1 = Enable DMA chaining interrupt */

           _DMAdis:1,     /* DMA chaining interrupt disable */
                          /*  0 = No effect */
                          /*  1 = Disable DMA chaining interrupt */

           _cmeena:1,     /* Correctable memory error interrupt enable */
                          /*  0 = No effect */
                          /*  1 = Enable CME interrupt */

           _cmedis:1,     /* Correctable memory error interrupt disable */
                          /*  0 = No effect */
                          /*  1 = Disable CME interrupt */

           _pad:2,        /* Reserved */

           _pad1:24;      /* Unused */
};

struct _l_eirqcontol_s {
    unsigned long _long;
};

union _eirqcontol_u {
    struct _b_read_eirqcontol_s  b_read_eirqcontol_s;
    struct _b_write_eirqcontol_s b_write_eirqcontol_s;
    struct _l_eirqcontol_s       l_eirqcontol_s;
};

struct eirqcontol_s {
    union _eirqcontol_u eirqcontol_u;
};

#define b_ncpact       eirqcontol_u.b_read_eirqcontol_s._ncpact
#define b_ncpstart     eirqcontol_u.b_read_eirqcontol_s._ncpstat
#define b_DMAact       eirqcontol_u.b_read_eirqcontol_s._DMAact
#define b_DMAstart     eirqcontol_u.b_read_eirqcontol_s._DMAstat
#define b_cmeact       eirqcontol_u.b_read_eirqcontol_s._cmeact
#define b_cmestart     eirqcontol_u.b_read_eirqcontol_s._cmestat
#define b_ncpena       eirqcontol_u.b_write_eirqcontol_s._ncpena
#define b_ncpdis       eirqcontol_u.b_write_eirqcontol_s._ncpdis
#define b_DMAena       eirqcontol_u.b_write_eirqcontol_s._DMAena
#define b_DMAdis       eirqcontol_u.b_write_eirqcontol_s._DMAdis
#define b_cmeena       eirqcontol_u.b_write_eirqcontol_s._cmeena
#define b_cmedis       eirqcontol_u.b_write_eirqcontol_s._cmedis
#define b_eirq_all     eirqcontol_u.l_eirqcontol_s._long


