### Predefined Make Utility Macros

Two types of macros are predefined:

File Specification Macros, and
Command Macros

File specification macros return one or more file specifications for the files in the target/dependent line of a description block. Except where noted, the file specification includes the path of the file, the base file name, and the file-name extension.

File Specification Macro | Value
$@ | The complete specification of the target file
$* | The base name (without extension) of the target file. Path information is also returned if the path was specified as part of the target file name. This macro cannot be used in a dependent list.
$** | The specifications of the dependent files.
$? | The specifications for only those dependent files that are out-of-date with respect to the targets.
$< | The specification of a single dependent file that is out-of-date with respect to the targets. This macro is used only in inference rules.
$$@ | The file specification of the target that NMAKE is currently evaluating. This is a dynamic dependency parameter, used only in dependent lists.
Command Macro | Value
$(CC) | The string ICC, which is the command to run the IBM C and C++ Compilers. You can redefine this macro to use a different command.
$(AS) | The string MASM, which is the command to run the Macro Assembler (MASM). You can redefine this macro to use a different command.
$(MAKE) | The command name used to run the Make utility. This macro is used to invoke the utility recursively. If you redefine this macro, a warning message is issued. Note: The Make utility executes the command line in which $(MAKE) appears, even if the display commands option (/n) is on.
$(MAKEFLAG) | The Make utility options currently in effect. You cannot redefine this macro.

Note: The macros $** and $$@ are the only exceptions to the rule that macro names longer than one character must be enclosed in parentheses.

You can append characters to any of the first six macros in this list to modify the meaning of the macro. However, you cannot use macro substitutions in these macros.

Example of Predefined Make Utility Macros

>     TRIG.LIB : SIN.OBJ COS.OBJ ARCTAN.OBJ
>          !LIB TRIG.LIB -+$?;

In the example above, the macro $? represents the names of all dependent files that are out-of-date with respect to the target file. The exclamation point (!) preceding the LIB command causes the Make utility to execute the LIB command once for each dependent file in the list. As a result of this description, the LIB command is executed up to three times, each time replacing a module with a new version.

>     DIR=C:\INCLUDE
>     $(DIR)\GLOBALS.H : GLOBALS.H
>      COPY GLOBALS.H $@
>     $(DIR)\TYPES.H : TYPES.H
>      COPY TYPES.H $@
>     $(DIR)\MACROS.H : MACROS.H
>      COPY MACROS.H $@

The example above shows how to update a group of include files. Each of the files GLOBAL.H, TYPES.H, and MACROS.H in the directory C:\INCLUDE depends on its counterpart in the current directory. If one of the include files is out-of-date, the Make utility replaces it with the file of the same name from the current directory.

The following description file, which uses the special macro $$@, is equivalent:

>     DIR=C:\INCLUDE
>     $(DIR)\GLOBALS.H $(DIR)\TYPES.H $(DIR)\MACROS.H : $$(@F)
>     !COPY $? $@

The special macro $$(@F) signifies the file name (without the path) of the current target.

When the Make utility evaluates the description block, it evaluates the three targets, one at a time, with respect to their dependents. Thus the Make utility first checks whether C:\INCLUDE\GLOBALS.H is out-of-date compared with GLOBALS.H in the current directory. If so, it executes the command to copy the dependent file GLOBALS.H to the target. The Make utility repeats the procedure for the other two targets.

Note: On the command line, the macro $? refers to the dependent for this target. The macro $@ specifies the full file specification of the target file.

Modify File Specification Macros

Make Utility Macro Precedence Rules