### Substitution in a Make Utility Macro

Just as you use macros to substitute text within a description file, you use the following syntax to substitute text within a macro:

    $(macroname: string1 = string2)

Every occurrence of string1 is replaced by string2 in macroname. Spaces between the colon and string1 are considered part of string1. If string2 is a null string, all occurrences of string1 are deleted from the macro. The colon (:) must immediately follow macroname.

Note: The replacement of string1 with string2 in the macro is not a permanent change. If you use the macro again without a substitution, you get the original unchanged macro.

Example of Substitution in a Make Utility Macro

    	SOURCES = ONE.C TWO.C THREE.C
    	PROGRAM.EXE : $(SOURCES:.C=.OBJ)
    	LINK $**;

The example above defines a macro called SOURCES, which contains the names of three C source files. With this macro, the target/dependent line substitutes the .OBJ extension for the .C extension. Thus, the Make utility executes the following command:

    LINK ONE.OBJ TWO.OBJ THREE.OBJ;

Note: $** is a predefined macro that translates to all dependent files for a given target.

Make Utility Macros

Define a Make Utility Macro

Predefined Make Utility Macros